LQSPI_CFG (QSPI) Register Description
| Register Name | LQSPI_CFG |
|---|---|
| Offset Address | 0x00000000A0 |
| Absolute Address | 0x00FF0F00A0 (QSPI) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x000002EB |
| Description | Configuration |
Specifically for the Linear Quad-SPI Controller Note: Change register value only when controller is not communicating with the memory device. Software Driver name: XQSPIPS_LQSPI_CR
LQSPI_CFG (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| LQ_MODE | 31 | rwNormal read/write | 0x0 | Controller Select: 0: Generic Quad-SPI. 1: Legacy LQSPI, Linear Quad-SPI. Software Driver name: XQSPIPS_LQSPI_CR_LINEAR Note: Change this value only when controller is not communicating with the memory device. |
| TWO_MEM | 30 | rwNormal read/write | 0x0 | I/O Configuration: 0: One memory device. 1: Two memory devices. Software Driver name: XQSPIPS_LQSPI_CR_TWO_MEM Note: Change this value only when controller is not communicating with the memory device. |
| SEP_BUS | 29 | rwNormal read/write | 0x0 | I/O Configuration: 0: Single memory interface. 1: Separate memory intefaces. This bit only has meaning if [TWO_MEM] = 1. Software Driver name: XQSPIPS_LQSPI_CR_SEP_BUS Note: Change this value only when controller is not communicating with the memory device. |
| U_PAGE | 28 | rwNormal read/write | 0x0 | Upper Page Select: 0: Lower memory page. 1: Upper memory page. This bit only has meaning if there are 2 memory devices are present and single interface. i.e. when following are TRUE [TWO_MEM] = 1 (two devices) [SEP_BUS] = 0 (one interface) IO mode is not supported in LQSPI; [U_PAGE] selects the lower or upper memory for configuration or read/write operations. Note: Change this value only when controller is not communicating with the memory device. Software Driver name: XQSPIPS_LQSPI_CR_U_PAGE Note: Change this value only when controller is not communicating with the memory device. |
| ADDR_32BIT | 27 | rwNormal read/write | 0x0 | When this bit is set to one, lower 27 bits of AXI address appended with 5 zeroes in the MSB are used as address to the flash. When set to zero, lower 24 bits of AXI address on linear port are used as address to the flash. This is a static signal - should not be changed while controller is actively transmitting/receiving data to/from Flash device Note: Change this value only when controller is not communicating with the memory device. |
| Reserved | 26 | rwNormal read/write | 0x0 | reserved |
| MODE_EN | 25 | rwNormal read/write | 0x0 | IO mode is not supported in LQSPI; program this bit to 0. Software Driver name: XQSPIPS_LQSPI_CR_MODE_EN |
| MODE_ON | 24 | rwNormal read/write | 0x0 | IO mode is not supported in LQSPI; program this bit to 0. Software Driver name: XQSPIPS_LQSPI_CR_MODE_ON |
| MODE_BITS | 23:16 | rwNormal read/write | 0x0 | IO mode is not supported in LQSPI; program these bits to 0. Software Driver name: XQSPIPS_LQSPI_CR_MODE_BITS |
| Reserved | 15:11 | rwNormal read/write | 0x0 | Reserved, value is undefined when read. |
| DUMMY_BYTE | 10:8 | rwNormal read/write | 0x2 | Number of dummy bytes between address and return read data Software Driver name: XQSPIPS_LQSPI_CR_DUMMY |
| INST_CODE | 7:0 | rwNormal read/write | 0xEB | Read instruction code. The known read instruction codes are: 8'h03 - Read 8'h0B - Fast read 8'h3B - Fast read dual output 8'h6B - Fast read quad output 8'hBB - Fast read dual I/O 8'hEB - Fast read quad I/O 8'h13 - Four Byte Address Read 8'h0C - Four Byte Address Fast read 8'h3C - Four Byte Address Fast read dual output 8'h6C - Four Byte Address Fast read quad output 8'hBC - Four Byte Address Fast read dual I/O 8'hEC - Four Byte Address Fast read quad I/O Software Driver name: XQSPIPS_LQSPI_CR_INST |