DUMMY_CYCLE_EN (QSPI) Register Description
| Register Name | DUMMY_CYCLE_EN |
|---|---|
| Offset Address | 0x00000000C8 |
| Absolute Address | 0x00FF0F00C8 (QSPI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Dummy Cycles Enable |
DUMMY_CYCLE_EN (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
| DUMMY_CYCLE_EN | 0 | rwNormal read/write | 0x0 | Use DUMMY_CYCLES. This bit is applicable only in Linear mode. This bit should not be used in DMA mode. 0: Disable using dummy cycle value. 1: Enable using dummy cycle value. This is a static signal - should not be changed while controller is actively transmitting/receiving data to/from Flash device |