TRAN_EGRESS_DST_BASE_HI (AXIPCIE_EGRESS) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

TRAN_EGRESS_DST_BASE_HI (AXIPCIE_EGRESS) Register Description

Register NameTRAN_EGRESS_DST_BASE_HI
Offset Address0x000000001C
Absolute Address 0x00FD0E0C1C (AXIPCIE_EGRESS0)
0x00FD0E0C3C (AXIPCIE_EGRESS1)
0x00FD0E0C5C (AXIPCIE_EGRESS2)
0x00FD0E0C7C (AXIPCIE_EGRESS3)
0x00FD0E0C9C (AXIPCIE_EGRESS4)
0x00FD0E0CBC (AXIPCIE_EGRESS5)
0x00FD0E0CDC (AXIPCIE_EGRESS6)
0x00FD0E0CFC (AXIPCIE_EGRESS7)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEgress AXI Translation - Destination Address High

TRAN_EGRESS_DST_BASE_HI (AXIPCIE_EGRESS) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
egress_dst_base_hi31:0rwNormal read/write0x0egress_dst_base[63:32].