sys_cache_grp_sn_sam_cfg0_u_rnfbesam_nid76 (CPM5_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID: AM012
Release Date: 2023-08-29
Revision: 1.3

sys_cache_grp_sn_sam_cfg0_u_rnfbesam_nid76 (CPM5_CMN600) Register Description

Register Name	sys_cache_grp_sn_sam_cfg0_u_rnfbesam_nid76
Relative Address	0x0000968D48
Absolute Address	0x00FC968D48 (CPM5_CMN)
Width	64
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000000
Description	Configures top address bits for SN SAM system cache groups 0 and 1. All top_address_bit fields must be between bits 47 and 28. top_address_bit2 > top_address_bit1 > top_address_bit0.

sys_cache_grp_sn_sam_cfg0_u_rnfbesam_nid76 (CPM5_CMN600) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	63:46	razRead as zero	0x0	reserved
scg1_top_address_bit2	45:40	rwNormal read/write	0x0	Top address bit 2 for system cache group 1
Reserved	39:38	razRead as zero	0x0	reserved
scg1_top_address_bit1	37:32	rwNormal read/write	0x0	Top address bit 1 for system cache group 1
Reserved	31:30	razRead as zero	0x0	reserved
scg1_top_address_bit0	29:24	rwNormal read/write	0x0	Top address bit 0 for system cache group 1
Reserved	23:22	razRead as zero	0x0	reserved
scg0_top_address_bit2	21:16	rwNormal read/write	0x0	Top address bit 2 for system cache group 0
Reserved	15:14	razRead as zero	0x0	reserved
scg0_top_address_bit1	13:8	rwNormal read/write	0x0	Top address bit 1 for system cache group 0
Reserved	7:6	razRead as zero	0x0	reserved
scg0_top_address_bit0	5:0	rwNormal read/write	0x0	Top address bit 0 for system cache group 0