PL_EQ_TX_MAINCUR_5 (CPM4_PCIE1_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PL_EQ_TX_MAINCUR_5 (CPM4_PCIE1_ATTR) Register Description

Register NamePL_EQ_TX_MAINCUR_5
Relative Address0x0000000294
Absolute Address 0x00FCA60294 (CPM4_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionTx MAIN-Cursor for Preset5

This register should only be written to during reset of the PCIe block

PL_EQ_TX_MAINCUR_5 (CPM4_PCIE1_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 6:0rwNormal read/write0x0Tx MAIN-Cursor for Preset5