SMMU_CB25_TLBIVAAL_high (FPD_SMMU_TCU) Register Description
| Register Name | SMMU_CB25_TLBIVAAL_high |
|---|---|
| Relative Address | 0x000003962C |
| Absolute Address | 0x00FD83962C (FPD_SMMU_TCU) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation |
SMMU_CB25_TLBIVAAL_high (FPD_SMMU_TCU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ASID | 31:16 | woWrite-only | 0x0 | Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation |
| Address | 4:0 | woWrite-only | 0x0 | Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation |