por_dt_pmevcntCD_u_hnd_nid44 (CPM5_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_dt_pmevcntCD_u_hnd_nid44 (CPM5_CMN600) Register Description

Register Namepor_dt_pmevcntCD_u_hnd_nid44
Relative Address0x0000536010
Absolute Address 0x00FC536010 (CPM5_CMN)
Width64
TyperwNormal read/write
Reset Value0x00000000
DescriptionContains the PMU event counters C and D.

por_dt_pmevcntCD_u_hnd_nid44 (CPM5_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
pmevcntD63:32rwNormal read/write0x0PMU counter D
pmevcntC31:0rwNormal read/write0x0PMU counter C