TRCOSLSR (DBG_A721_ETM) Register Description
| Register Name | TRCOSLSR |
|---|---|
| Relative Address | 0x0000000304 |
| Absolute Address | 0x00F0D70304 (DBG_APU1_ETM) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x0000000A |
| Description | OS Lock Status Register |
TRCOSLSR (DBG_A721_ETM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| OSLM1 | 3 | roRead-only | 0x1 | Indicates that the OS Lock is implemented. |
| nTT | 2 | roRead-only | 0x0 | Indicates that software must perform a 32-bit write. |
| OSLK | 1 | roRead-only | 0x1 | OS Lock status bit: When the trace unit core power domain is powered down the value is UNKNOWN. The indicates if the trace unit core power domain is powered down. |
| OSLM0 | 0 | roRead-only | 0x0 | Indicates that the OS Lock is implemented. |