IP_Config11 (GEM) Register Description
| Register Name | IP_Config11 |
|---|---|
| Relative Address | 0x00000002A8 |
| Absolute Address |
0x00FF0C02A8 (GEM0) 0x00FF0D02A8 (GEM1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Design Implementation Reg 11 |
The controller implementation is defined in the DesignCfg_Debug [1:12] registers. All of these registers are read-only register; writes are ignored. Alternate register name: designcfg_debug11
IP_Config11 (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:5 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| protect_descr_addr | 4 | roRead-only | 0x0 | Takes the value of the `gem_protect_descr_addr DEFINE. |
| protect_tsu | 3 | roRead-only | 0x0 | Takes the value of the `gem_protect_tsu DEFINE. |
| add_csr_parity | 2 | roRead-only | 0x0 | Takes the value of the `gem_add_csr_parity DEFINE. |
| add_dp_parity | 1 | roRead-only | 0x0 | Takes the value of the `gem_add_dp_parity DEFINE. |
| add_ecc_dpram | 0 | roRead-only | 0x0 | Takes the value of the `gem_add_ecc_dpram DEFINE. |