PMEVTYPER24 (FPD_SMMU_TCU) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PMEVTYPER24 (FPD_SMMU_TCU) Register Description

Register NamePMEVTYPER24
Relative Address0x0000003460
Absolute Address 0x00FD803460 (FPD_SMMU_TCU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionProvides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter

PMEVTYPER24 (FPD_SMMU_TCU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
P31rwNormal read/write0Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
U30rwNormal read/write0Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
NSP29rwNormal read/write0Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
NSU28rwNormal read/write0Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
EVENT 4:0rwNormal read/write0Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter