| Field Name | Bits | Type | Reset Value | Description |
|---|
| pcie_ccix_rate_chg_irq | 8 | wtcReadable, write a 1 to clear | 0x0 | Status of interrupt for PCIe CCIX rate change to/from 20G or 25G |
| pcie_agfm_irq | 7 | wtcReadable, write a 1 to clear | 0x0 | Status of interrupt for DMA user clock auto switch event |
| perst_rcvd | 6 | wtcReadable, write a 1 to clear | 0x0 | Status of IO Reset to PCIe core interrupt |
| pcie_ccix_pdvsec_cfg_wr_rcvd | 5 | wtcReadable, write a 1 to clear | 0x0 | Status of dvsec cfg write interrupt |
| pcie_ccix_pdvsec_cfg_rd_rcvd | 4 | wtcReadable, write a 1 to clear | 0x0 | Status of dvsec cfg read interrupt |
| pcie_cfg_msg_received | 3 | wtcReadable, write a 1 to clear | 0x0 | Status for cfg message received interrupt |
| pcie_msi1 | 2 | wtcReadable, write a 1 to clear | 0x0 | Status for MSI received interrupt with vector 32-63 set, RP only. To decode this interrupt further, software must read XDMA_REG.MSI_DEC_63_32 register |
| pcie_msi0 | 1 | wtcReadable, write a 1 to clear | 0x0 | Status for MSI received interrupt with vector 0-31 set, RP only. To decode this interrupt further, software must read XDMA_REG.MSI_DEC_31_0 register |
| pcie_local_event | 0 | wtcReadable, write a 1 to clear | 0x0 | Status for PCIe local interrupt events and errors. To decode the reason for this interrupt, software must read XDMA_REG.INT_DEC register. |