por_ppu_int_status_u_hnd_nid44 (CPM5_CMN600) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

por_ppu_int_status_u_hnd_nid44 (CPM5_CMN600) Register Description

Register Namepor_ppu_int_status_u_hnd_nid44
Relative Address0x0000505008
Absolute Address 0x00FC505008 (CPM5_CMN)
Width64
TyperwNormal read/write
Reset Value0x00000000
DescriptionProvides HN-F PPU event interrupt status.

por_ppu_int_status_u_hnd_nid44 (CPM5_CMN600) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
hnf_ppu_status63:0rwNormal read/write0x0Interrupt status