I2C_IMR (PS_I2C) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

I2C_IMR (PS_I2C) Register Description

Register NameI2C_IMR
Relative Address0x0000000020
Absolute Address 0x00FF020020 (LPD_I2C0)
0x00FF030020 (LPD_I2C1)
Width16
TyperoRead-only
Reset Value0x000002FF
DescriptionInterrupt Mask

Interrupt mask bit states: 0: unmask (enable interrupt) 1: set mask (disable interrupt, reset default) Note: Read-only. Set the IMR bits by writing ones to the IDR register. Clear the IMR bits by writing ones to the IER register. Note: These interrupts are described with the ISR status register and in the TRM. Alternate register name: Intrpt_mask_reg0

I2C_IMR (PS_I2C) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved15:10roRead-only0x0reserved
ARB_LOST 9roRead-only0x1Arbitration Lost
Reserved 8roRead-only0x0reserved
RX_UNF 7roRead-only0x1FIFO receive underflow
TX_OVF 6roRead-only0x1FIFO transmit overflow
RX_OVF 5roRead-only0x1Receive overflow
SLV_RDY 4roRead-only0x1Monitored slave ready
TO 3roRead-only0x1Transfer time out
NACK 2roRead-only0x1Transfer not acknowledged
DATA 1roRead-only0x1More data
COMP 0roRead-only0x1Transfer complete