DELAYED_FLR (CPM4_PCIE1_ATTR) Register Description
| Register Name | DELAYED_FLR |
|---|---|
| Relative Address | 0x000000072C |
| Absolute Address | 0x00FCA6072C (CPM4_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | When FALSE: Original FLR behavior. When TRUE: New FLR behavior. Resetting of registers in the target function is delayed until after user response (cfg_flr_done, cfg_vf_flr_done) is r received. |
This register should only be written to during reset of the PCIe block
DELAYED_FLR (CPM4_PCIE1_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 | When FALSE: Original FLR behavior. When TRUE: New FLR behavior. Resetting of registers in the target function is delayed until after user response (cfg_flr_done, cfg_vf_flr_done) is r received. |