PM_ASPML0S_TIMEOUT (CPM5_PCIE_ATTR) Register Description
| Register Name | PM_ASPML0S_TIMEOUT |
|---|---|
| Relative Address | 0x00000000C8 |
| Absolute Address |
0x00FCE080C8 (CPM5_PCIE0_ATTR) 0x00FCE880C8 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | L0S Timeout Limit Register: Timeout value for transitioning to the L0S power state. If the transmit side has been idle for this interval, the core will transmit the idle sequence on the link and transition the state of the link to L0S. Contains the timeout value for transitioning to the L0S power state Setting it to 0 permanently disables the transition to the L0S power state. When CRM_CORE_CLK_FREQ == 00100b Time unit = 1ns, for all other CRM_CORE_CLK_FREQ Time unit = 2ns |
This register should only be written to during reset of the PCIe block
PM_ASPML0S_TIMEOUT (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 15:0 | rwNormal read/write | 0x0 | L0S Timeout Limit Register: Timeout value for transitioning to the L0S power state. If the transmit side has been idle for this interval, the core will transmit the idle sequence on the link and transition the state of the link to L0S. Contains the timeout value for transitioning to the L0S power state Setting it to 0 permanently disables the transition to the L0S power state. When CRM_CORE_CLK_FREQ == 00100b Time unit = 1ns, for all other CRM_CORE_CLK_FREQ Time unit = 2ns |