C2H3_CHANNEL_PERFORMANCE_MONITOR_CONTROL (CPM4_XDMA_CSR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID: AM012
Release Date: 2023-08-29
Revision: 1.3

C2H3_CHANNEL_PERFORMANCE_MONITOR_CONTROL (CPM4_XDMA_CSR) Register Description

Register Name	C2H3_CHANNEL_PERFORMANCE_MONITOR_CONTROL
Relative Address	0x00000013C0
Absolute Address	0x00E10013C0 (CPM4_XDMA_CSR)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000000
Description	C2H3_CHANNEL_PERFORMANCE_MONITOR_CONTROL

C2H3_CHANNEL_PERFORMANCE_MONITOR_CONTROL (CPM4_XDMA_CSR) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	31:4	roRead-only	0x0
now	3	rwNormal read/write	0x0	Set to 1 to start performance counters immediately
run	2	rwNormal read/write	0x0	Set to 1 to arm performance counters. Counter starts after the Control.Run (Byte offset 0x1) bit is set. Set to 0 to halt performance counters.
clear	1	woWrite-only	0x0	Write 1 to clear performance counters.
auto	0	rwNormal read/write	0x0	Automatically stop performance counters when a descriptor with the stop bit is completed. Automatically clear performance counters when the Control.Run (Byte offset 0x1) is set. Writing 1 to PerformanceControl.Run is still required to start the counters.