div_override (CPM5_PCIE_CSR) Register Description
| Register Name | div_override |
|---|---|
| Relative Address | 0x00000002A0 |
| Absolute Address |
0x00FCE002A0 (CPM5_PCIE0_CSR) 0x00FCE802A0 (CPM5_PCIE1_CSR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | div_override |
div_override (CPM5_PCIE_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| rstmask | 22:19 | rwNormal read/write | 0x0 | reset mask |
| rst | 18 | rwNormal read/write | 0x0 | reset |
| cemask | 17:14 | rwNormal read/write | 0x0 | clock enable mask |
| ce | 13 | rwNormal read/write | 0x0 | clock enable |
| div | 12:1 | rwNormal read/write | 0x0 | divisor value |
| enable | 0 | rwNormal read/write | 0x0 | If enable=1, divider that is used to generate PCIe clocks will be controlled by this register and not from GT. |