FLAG (UART) Register Description
| Register Name | FLAG |
|---|---|
| Relative Address | 0x0000000018 |
| Absolute Address |
0x00FF000018 (UART0) 0x00FF010018 (UART1) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000090 |
| Description | Interface Flags |
Alternate register name: UARTFR
FLAG (UART) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:9 | rwNormal read/write | 0x0 | Reserved, do not modify, read as zero. |
| RI | 8 | rwNormal read/write | 0x0 | Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. |
| TXFE | 7 | rwNormal read/write | 0x1 | Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. |
| RXFF | 6 | rwNormal read/write | 0x0 | Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. |
| TXFF | 5 | rwNormal read/write | 0x0 | Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. |
| RXFE | 4 | rwNormal read/write | 0x1 | Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. |
| BUSY | 3 | rwNormal read/write | 0x0 | UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. |
| DCD | 2 | rwNormal read/write | 0x0 | Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. |
| DSR | 1 | rwNormal read/write | 0x0 | Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. |
| CTS | 0 | rwNormal read/write | 0x0 | Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. |