TRCTSCTLR (DBG_A720_ETM) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

TRCTSCTLR (DBG_A720_ETM) Register Description

Register NameTRCTSCTLR
Relative Address0x0000000030
Absolute Address 0x00F0D30030 (DBG_APU0_ETM)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionGlobal Timestamp Control Register

TRCTSCTLR (DBG_A720_ETM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
EVENT 7:0rwNormal read/write0An event selector. When the selected event is triggered, the trace unit inserts a global timestamp into the trace streams.