ADV_SWTm_EXPANSION_ROM_ENABLE_2 (CPM5_PCIE_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

ADV_SWTm_EXPANSION_ROM_ENABLE_2 (CPM5_PCIE_ATTR) Register Description

Register NameADV_SWTm_EXPANSION_ROM_ENABLE_2
Relative Address0x00000024E8
Absolute Address 0x00FCE0A4E8 (CPM5_PCIE0_ATTR)
0x00FCE8A4E8 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionExpansion ROM BAR Enable: This bit must be set to enable the Expansion ROM BAR associated with the Function.

This register should only be written to during reset of the PCIe block

ADV_SWTm_EXPANSION_ROM_ENABLE_2 (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0Expansion ROM BAR Enable: This bit must be set to enable the Expansion ROM BAR associated with the Function.