ADV_SWT_DSPn_BAR1_CONTROL_9 (CPM5_PCIE_ATTR) Register Description
| Register Name | ADV_SWT_DSPn_BAR1_CONTROL_9 |
|---|---|
| Relative Address | 0x0000002824 |
| Absolute Address |
0x00FCE0A824 (CPM5_PCIE0_ATTR) 0x00FCE8A824 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | BAR1 DSP Control - Specifies the configuration of BAR 1. The various encodings are: 000: Disabled 001: 32-bit IO BAR 010-011: Reserved 100: 32-bit memory BAR, non-prefetchable 101: 32-bit memory BAR, prefetchable |
This register should only be written to during reset of the PCIe block
ADV_SWT_DSPn_BAR1_CONTROL_9 (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 2:0 | rwNormal read/write | 0x0 | BAR1 DSP Control - Specifies the configuration of BAR 1. The various encodings are: 000: Disabled 001: 32-bit IO BAR 010-011: Reserved 100: 32-bit memory BAR, non-prefetchable 101: 32-bit memory BAR, prefetchable |