SMMU_CB26_PMCNTENSET (FPD_SMMU_TCU) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

SMMU_CB26_PMCNTENSET (FPD_SMMU_TCU) Register Description

Register NameSMMU_CB26_PMCNTENSET
Relative Address0x000003AF48
Absolute Address 0x00FD83AF48 (FPD_SMMU_TCU)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionProvides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter

SMMU_CB26_PMCNTENSET (FPD_SMMU_TCU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
P3 3woWrite-only0Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
P2 2woWrite-only0Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
P1 1woWrite-only0Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
P0 0woWrite-only0Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter