SBI_CTRL (PMC_SBI_CSR) Register Description
| Register Name | SBI_CTRL |
|---|---|
| Relative Address | 0x0000000004 |
| Absolute Address | 0x00F1220004 (PMC_SBI_CSR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000020 |
| Description | SBI Control Register |
SBI_CTRL (PMC_SBI_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:6 | razRead as zero | 0x0 | Reserved for future use |
| apb_err_res | 5 | rwNormal read/write | 0x1 | When an APB (register) access occurs to an unimplemented space (there is no register at that location), the resulting pslverr will be: 0 - pslverr Disable 1 - pslverr Enable There is also a maskable interrupt , "INV_APB" that could be asserted, independent of what option is selected here. |
| interface | 4:2 | rwNormal read/write | 0x0 | Select Slave Boot Interface to transfer data 000 - SelectMap Mode data transfer 001 - JTAG Mode data transfer 010 - AXI Slave data transfer (Only supported in configuration mode) 011 - AXI HSDP Slave data transfer (Only supported in configuration mode) 100 - Reserved 101 - Reserved 110 - Reserved 111 - Reserved |
| Reserved | 1 | rwNormal read/write | 0x0 | reserved, write 0 Note: Field name reference: soft_rst |
| enable | 0 | rwNormal read/write | 0x0 | Slave Boot Interface enable/disable control 0 - Disable 1 - Enable |