TZ_PCIE1 (CPM5_SLCR_SECURE) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

TZ_PCIE1 (CPM5_SLCR_SECURE) Register Description

Register NameTZ_PCIE1
Relative Address0x0000000104
Absolute Address 0x00FCDE0104 (CPM5_SLCR_SECURE)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000003
DescriptionTrustZone Classification for PCIe1
1: Non-Secure
0: Secure

This register should only be written to while the target block is in reset.

TZ_PCIE1 (CPM5_SLCR_SECURE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2roRead-only0x0Reserved
attrib_pcie 1rwNormal read/write0x1PCIe1 attribute registers
cfg_mgmt_pcie 0rwNormal read/write0x1security for cfg mgmt slave (dvsec paths) for PCIe Core 1