TRCSYNCPR (DBG_A720_ETM) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

TRCSYNCPR (DBG_A720_ETM) Register Description

Register NameTRCSYNCPR
Relative Address0x0000000034
Absolute Address 0x00F0D30034 (DBG_APU0_ETM)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSynchronization Period Register

TRCSYNCPR (DBG_A720_ETM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PERIOD 4:0rwNormal read/write0Controls how many bytes of trace, the sum of instruction and data, that a trace unit can generate before a periodic trace synchronization request occurs. The number of bytes is a power of two of this field, and the permitted values are from 16 to 20. Values between 1 and 15 are reserved, as are values from 21 onwards.