Multiple_Collisions_Count (GEM) Register Description
| Register Name | Multiple_Collisions_Count |
|---|---|
| Relative Address | 0x000000013C |
| Absolute Address |
0x00FF0C013C (GEM0) 0x00FF0D013C (GEM1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Multiple Collision Frames |
Alternate register name: multiple_collisions
Multiple_Collisions_Count (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:18 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| count | 17:0 | roRead-only | 0x0 | Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no under run and not too many retries. |