PF1_CCIX_PDVSEC_PCSR_START_ADDR (CPM5_PCIE_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PF1_CCIX_PDVSEC_PCSR_START_ADDR (CPM5_PCIE_ATTR) Register Description

Register NamePF1_CCIX_PDVSEC_PCSR_START_ADDR
Relative Address0x0000001E54
Absolute Address 0x00FCE09E54 (CPM5_PCIE0_ATTR)
0x00FCE89E54 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPF1 CCIX Protocol DVSEC CSR Region Start Address

This register should only be written to during reset of the PCIe block

PF1_CCIX_PDVSEC_PCSR_START_ADDR (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr11:0rwNormal read/write0x0PF1 CCIX Protocol DVSEC CSR Region Start Address