PWR_STATE (PSM_GLOBAL) Register Description
| Register Name | PWR_STATE |
|---|---|
| Relative Address | 0x0000000100 |
| Absolute Address | 0x00FFC90100 (PSM_GLOBAL) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x003FFC83 |
| Description | Power Island and LPD-FPD Isolation States |
This register shows the power state of several power islands plus the isolation status for the LPD-FPD boundary. 0: powered-down 1: powered-up Note: This register is only reset by the Power-on Reset (POR) and maintains its value through a System Reset (SRST)
PWR_STATE (PSM_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:23 | roRead-only | 0x0 | Reserved |
| FP | 22 | roRead-only | 0x0 | Power Isolation State for FP Domain. It is marked as off if functional signal isolation between FPD and LPD is enabled. |
| GEM0 | 21 | roRead-only | 0x1 | Power State for GEM0 |
| GEM1 | 20 | roRead-only | 0x1 | Power State for GEM1 |
| OCM_Bank3 | 19 | roRead-only | 0x1 | Power State for OCM_Bank3 |
| OCM_Bank2 | 18 | roRead-only | 0x1 | Power State for OCM_Bank2 |
| OCM_Bank1 | 17 | roRead-only | 0x1 | Power State for OCM_Bank1 |
| OCM_Bank0 | 16 | roRead-only | 0x1 | Power State for OCM_Bank0 |
| TCM1B | 15 | roRead-only | 0x1 | TCM power island state |
| TCM1A | 14 | roRead-only | 0x1 | TCM power island state |
| TCM0B | 13 | roRead-only | 0x1 | TCM power island state |
| TCM0A | 12 | roRead-only | 0x1 | TCM power island state Note: All four TCM power islands are requred to be active to access any of the TCMs; normally, all four islands are On OR all four islands are Off. |
| R5_1 | 11 | roRead-only | 0x1 | Power State for R5_1 |
| R5_0 | 10 | roRead-only | 0x1 | Power State for R5_0 |
| Reserved | 9:8 | roRead-only | 0x0 | Reserved |
| L2_Bank0 | 7 | roRead-only | 0x1 | Power State for L2_Bank0 |
| Reserved | 6:2 | roRead-only | 0x0 | Reserved |
| ACPU1 | 1 | roRead-only | 0x1 | Power State for ACPU1 |
| ACPU0 | 0 | roRead-only | 0x1 | Power State for ACPU0 |