PL_RX_ADAPT_TIMER_CLWS_GEN3 (CPM4_PCIE1_ATTR) Register Description
| Register Name | PL_RX_ADAPT_TIMER_CLWS_GEN3 |
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| Relative Address | 0x00000001BC |
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| Absolute Address |
0x00FCA601BC (CPM4_PCIE1_ATTR)
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| Width | 32 |
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| Type | rwNormal read/write |
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| Reset Value | 0x00000000 |
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| Description | Xilinx GT implementation Specific Rx Adaptation Timeout state before Configuration.LinkWidthStart when current speed is Gen3 (in milli seconds). Value of 0h disables the timer. Allowed values are 0h to Fh |
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This register should only be written to during reset of the PCIe block
PL_RX_ADAPT_TIMER_CLWS_GEN3 (CPM4_PCIE1_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| attr | 3:0 | rwNormal read/write | 0x0 | Xilinx GT implementation Specific Rx Adaptation Timeout state before Configuration.LinkWidthStart when current speed is Gen3 (in milli seconds). Value of 0h disables the timer. Allowed values are 0h to Fh |