CCF_MASK (RPU_DUAL_CSR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

CCF_MASK (RPU_DUAL_CSR) Register Description

Register NameCCF_MASK
Relative Address0x0000000024
Absolute Address 0x00FF9A0024 (RPU_DUAL_CSR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionCommon Cause Signal (CCF)
Mask

0: signal is masked 1: signal is not masked Alternate register name: RPU_CCF_MASK

CCF_MASK (RPU_DUAL_CSR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0reserved
test_mbist_mode 7rwNormal read/write0x0MBIST enable
test_scan_mode_lp 6rwNormal read/write0x0Power island scan enable
test_scan_mode 5rwNormal read/write0x0Scan enable
iso 4rwNormal read/write0x0Isolation enable
pge 3rwNormal read/write0x0Power island enable
r50_dbg_rst 2rwNormal read/write0x0RPU CPU0 debug reset
r50_rst 1rwNormal read/write0x0RPU0 CPU reset
pge_rst 0rwNormal read/write0x0Power island reset