PF0_DEV_CAP2_10B_TAG_COMPLETER_SUPPORTED (CPM5_PCIE_ATTR) Register Description
| Register Name | PF0_DEV_CAP2_10B_TAG_COMPLETER_SUPPORTED |
|---|---|
| Relative Address | 0x0000001E6C |
| Absolute Address |
0x00FCE09E6C (CPM5_PCIE0_ATTR) 0x00FCE89E6C (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | 10-Bit Tag Completer Supported: When TRUE all Functions supports 10-Bit Tag Completer capability; otherwise, the Functions do not. |
This register should only be written to during reset of the PCIe block
PF0_DEV_CAP2_10B_TAG_COMPLETER_SUPPORTED (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 | 10-Bit Tag Completer Supported: When TRUE all Functions supports 10-Bit Tag Completer capability; otherwise, the Functions do not. |