PF0_DEV_CAP_ENDPOINT_L1_LATENCY (CPM5_PCIE_ATTR) Register Description
| Register Name | PF0_DEV_CAP_ENDPOINT_L1_LATENCY |
|---|---|
| Relative Address | 0x0000000DDC |
| Absolute Address |
0x00FCE08DDC (CPM5_PCIE0_ATTR) 0x00FCE88DDC (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices. |
This register should only be written to during reset of the PCIe block
PF0_DEV_CAP_ENDPOINT_L1_LATENCY (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 2:0 | rwNormal read/write | 0x0 | Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices. |