C2H3_CHANNEL_INTERRUPT_ENABLE_MASK_WTC (CPM4_XDMA_CSR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

C2H3_CHANNEL_INTERRUPT_ENABLE_MASK_WTC (CPM4_XDMA_CSR) Register Description

Register NameC2H3_CHANNEL_INTERRUPT_ENABLE_MASK_WTC
Relative Address0x0000001398
Absolute Address 0x00E1001398 (CPM4_XDMA_CSR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionC2H3_CHANNEL_INTERRUPT_ENABLE_MASK_WTC

C2H3_CHANNEL_INTERRUPT_ENABLE_MASK_WTC (CPM4_XDMA_CSR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:24roRead-only0x0
im_desc_error23:19wtcReadable, write a 1 to clear0x0Set to 1 to interrupt when corresponding status register read_error bit is logged.
im_read_error13:9wtcReadable, write a 1 to clear0x0set to 1 to interrupt when corresponding status register read_error bit is logged.
Reserved 8:7wtcReadable, write a 1 to clear0x0
im_idle_stopped 6wtcReadable, write a 1 to clear0x0Set to 1 to interrupt when the status register idle_stopped bit is logged.
im_invalid_length 5wtcReadable, write a 1 to clear0x0Set to 1 to interrupt when status register align_mismatch bit is logged.
im_magic_stopped 4wtcReadable, write a 1 to clear0x0Set to 1 to interrupt when status register magic_stopped bit is logged.
im_align_mismatch 3wtcReadable, write a 1 to clear0x0Set to 1 to interrupt when status register align_mismatch bit is logged.
im_descriptor_completd 2wtcReadable, write a 1 to clear0x0Set to 1 to interrupt when status register descriptor_completed bit is logged.
im_descriptor_stopped 1wtcReadable, write a 1 to clear0x0Set to 1 to interrupt when status register descriptor_stopped bit is logged.
Reserved 0roRead-only0x0