CLKMON_STATUS (CPM5_SLCR) Register Description
| Register Name | CLKMON_STATUS |
|---|---|
| Relative Address | 0x0000000120 |
| Absolute Address | 0x00FCDD0120 (CPM5_SLCR) |
| Width | 16 |
| Type | wtcReadable, write a 1 to clear |
| Reset Value | 0x00000000 |
| Description | Interrupt Status Register for all Clock Monitors. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
CLKMON_STATUS (CPM5_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| cnta_over_err | 1 | wtcReadable, write a 1 to clear | 0x0 | Overflow for counter that is clocked by clock A. |
| mon_err | 0 | wtcReadable, write a 1 to clear | 0x0 | CLK0 was not within the acceptable range |