PFx_SRIOV_BAR5_CONTROL_14 (CPM5_PCIE_ATTR) Register Description
Register Name | PFx_SRIOV_BAR5_CONTROL_14 |
---|---|
Relative Address | 0x0000001A04 |
Absolute Address |
0x00FCE09A04 (CPM5_PCIE0_ATTR) 0x00FCE89A04 (CPM5_PCIE1_ATTR) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | VF BAR5 Control - Specifies the configuration of BAR 5 when it is configured as a 32-bit BAR. The various encodings are: 000: Disabled 001-011: Reserved 100: 32-bit memory BAR, non-prefetchable 101: 32-bit memory BAR, prefetchable |
This register should only be written to during reset of the PCIe block
PFx_SRIOV_BAR5_CONTROL_14 (CPM5_PCIE_ATTR) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr | 2:0 | rwNormal read/write | 0x0 | VF BAR5 Control - Specifies the configuration of BAR 5 when it is configured as a 32-bit BAR. The various encodings are: 000: Disabled 001-011: Reserved 100: 32-bit memory BAR, non-prefetchable 101: 32-bit memory BAR, prefetchable |