IR_ENABLE (CPM5_SLCR_SECURE) Register Description
| Register Name | IR_ENABLE |
|---|---|
| Relative Address | 0x0000000018 |
| Absolute Address | 0x00FCDE0018 (CPM5_SLCR_SECURE) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
IR_ENABLE (CPM5_SLCR_SECURE) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | roRead-only | 0x0 | Reserved |
| addr_decode_err | 0 | woWrite-only | 0x0 | Enable for an address decode error interrupt. |