| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:5 | rwNormal read/write | 0x0 | 1b1 indicates that the reset is released. When reset =1b0, it resets the NIU corresponding to the slave. It needs to be ensured that when the reset is asserted(1b0), the respective slave(s) also get reset to ensure error free flow once reset gets released |
| raw_rst_n | 4 | rwNormal read/write | 0x1 | 1b1 indicates that the reset is released. When reset =1b0, it resets the NIU corresponding to the slave. It needs to be ensured that when the reset is asserted(1b0), the respective slave(s) also get reset to ensure error free flow once reset gets released |
| power_idlereq | 3 | rwNormal read/write | 0x0 | Writing 1b1 initiates a slave isolation request to the corresponding SERB. |
| power_idleack | 2 | roRead-only | 0x1 | 1b1 indicates idle request has been detected. 1b0 indicates idle request has not been detected. NIU reset needs to be enabled to clear this bit. |
| power_idle | 1 | roRead-only | 0x1 | 1b1 indicates slave(s) has been isolated. 1b0 indicates slave(s) has not been isolated. The reset needs to be asserted to clear this bit. |
| mainexten | 0 | rwNormal read/write | 0x0 | Register to Enable/Disable the SERB Timeout counter. 1b1 enables the SERB to start counting 2K clock cycles (4k edges) before repoting a timeout interrupt. 1b0 disables this counting resulting in SERB not timing out for an incomplete transaction |