H2C1_CHANNEL_COMPLETED_DESCRIPTOR_COUNT (CPM4_XDMA_CSR) Register Description
| Register Name | H2C1_CHANNEL_COMPLETED_DESCRIPTOR_COUNT |
|---|---|
| Relative Address | 0x0000000148 |
| Absolute Address | 0x00E1000148 (CPM4_XDMA_CSR) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | H2C1_CHANNEL_COMPLETED_DESCRIPTOR_COUNT |
H2C1_CHANNEL_COMPLETED_DESCRIPTOR_COUNT (CPM4_XDMA_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| compl_descriptor_count | 31:0 | roRead-only | 0x0 | This register is incremented after each descriptor has completed. It is reset to 0 on rising edge of Control register, run bit. |