control_n_enable_c_n (RPU_GIC_PL390) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

control_n_enable_c_n (RPU_GIC_PL390) Register Description

Register Namecontrol_n_enable_c_n
Relative Address0x0000001054
Absolute Address 0x00F9001054 (RPU_GIC_PL390)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionReturns the status of the enable_c<n> tie-off signals for CPU
Interface <n>.

control_n_enable_c_n (RPU_GIC_PL390) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
enable_c31:0roRead-only0x0Returns the status of the enable_c<n>[31:0] inputs for CPU
Interface <n>:
Bit [X] = 0 enable_c<n>[x] is LOW
Bit [X] = 1 enable_c<n>[x] is HIGH.
Where <n> is a number, from 0 to 7. that identifies one of
the CPU Interfaces.