rpu0_lpd_axi_power_main_ResilienceFaultController_MissionFault0 (LPD_INT_GPV) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

rpu0_lpd_axi_power_main_ResilienceFaultController_MissionFault0 (LPD_INT_GPV) Register Description

Register Namerpu0_lpd_axi_power_main_ResilienceFaultController_MissionFault0
Relative Address0x0000001908
Absolute Address 0x00FE401908 (LPD_INT_GPV)
Width32
TyperoRead-only
Reset Value0x00000000
Descriptionrpu0_lpd_axi_power_main_ResilienceFaultController_MissionFault0

Alternate register name: rpu0_lpd_axi_power_main_ResilienceFaultController_MissionFault0

rpu0_lpd_axi_power_main_ResilienceFaultController_MissionFault0 (LPD_INT_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MissionFault031:3roRead-only0x0MissionFault0 register - Spares
rpu0_lpd_axi_power_main 2roRead-only0x0MissionFault0 register for rpu0_lpd_axi_power_main has 2 possible sources for trigger
if_rpu0_intlpd_axi_rd_I_main 1roRead-only0x0MissionFault0 register for if_rpu0_intlpd_axi_rd_I_main has 4 possible sources for trigger
if_rpu0_intlpd_axi_wr_I_main 0roRead-only0x0MissionFault0 register for if_rpu0_intlpd_axi_wr_I_main has 4 possible sources for trigger