SMMU_NSTLBGSYNC (FPD_SMMU_TCU) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

SMMU_NSTLBGSYNC (FPD_SMMU_TCU) Register Description

Register NameSMMU_NSTLBGSYNC
Relative Address0x0000000470
Absolute Address 0x00FD800470 (FPD_SMMU_TCU)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionStarts a global synchronization operation that ensures the completion of any previously accepted TLB Invalidate operation. As a minimum, the operation applies to the specified security state, and includes all TLB Invalidate operations initiated in context banks associated with that security state.

SMMU_NSTLBGSYNC (FPD_SMMU_TCU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
bits31:0woWrite-only0Starts a global synchronization operation that ensures the completion of any previously accepted TLB Invalidate operation. As a minimum, the operation applies to the specified security state, and includes all TLB Invalidate operations initiated in context banks associated with that security state.