attr_dma_ch1_xdma_c2h_aximm_steering (CPM5_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

attr_dma_ch1_xdma_c2h_aximm_steering (CPM5_DMA_ATTR) Register Description

Register Nameattr_dma_ch1_xdma_c2h_aximm_steering
Relative Address0x00000002EC
Absolute Address 0x00FCE102EC (CPM5_DMA0_ATTR)
0x00FCE902EC (CPM5_DMA1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
Descriptionxdma C2H AXIMM Steering

This register should only be written to during reset of the PCIe block

attr_dma_ch1_xdma_c2h_aximm_steering (CPM5_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 3:0rwNormal read/write0x0xdma C2H AXIMM Steering