| Field Name | Bits | Type | Reset Value | Description |
|---|
| LC | 6 | rwNormal read/write | 0x0 | Long cycle counter enable. Determines which PMCCNTR_EL0 bit ( bit 63 or bit 31) generates an overflow recorded by PMOVSR[31]. |
| DP | 5 | rwNormal read/write | 0x0 | Disable cycle counter when event counting is prohibited. |
| X | 4 | rwNormal read/write | 0x0 | Enable export of events in an event stream. |
| D | 3 | rwNormal read/write | 0x0 | Clock divider. When 0, PMCCNTR_EL0 counts every clock cycle; when 1, PMCCNTR_EL0 counts every 64 clock cycles. |
| C | 2 | woWrite-only | 0x0 | Cycle counter reset. This bit is WO and RAZ. Writing 1 resets PMCCNTR_EL0 to zero, but does not clear the PMCCNTR_EL0 overflow bit. |
| P | 1 | woWrite-only | 0x0 | Event counter reset. This bit is WO and RAZ.
Writing 1 resets all evert counters (not including PMCCNTR_EL0), but does not clear any overflow bits. |
| E | 0 | rwNormal read/write | 0x0 | Enable. When 1, all counters are enbled by PMCNTENSET_EL0; when 0, all counters including PMCCNTR_EL0 are disabled. |