attr_dma_axibar2pciebar_3_h (CPM5_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

attr_dma_axibar2pciebar_3_h (CPM5_DMA_ATTR) Register Description

Register Nameattr_dma_axibar2pciebar_3_h
Relative Address0x0000000254
Absolute Address 0x00FCE10254 (CPM5_DMA0_ATTR)
0x00FCE90254 (CPM5_DMA1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAXI to PCIe bar translation

This register should only be written to during reset of the PCIe block

attr_dma_axibar2pciebar_3_h (CPM5_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr31:0rwNormal read/write0x0AXI to PCIe bar translation