CE_INT_TIMEOUT_IMR (XRAM_SLCR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

CE_INT_TIMEOUT_IMR (XRAM_SLCR) Register Description

Register NameCE_INT_TIMEOUT_IMR
Relative Address0x000000A188
Absolute Address 0x00FF95A188 (XRAM_SLCR)
Width32
TyperoRead-only
Reset Value0x000001FF
DescriptionInterrupt mask register for correctable timeout slave errors

CE_INT_TIMEOUT_IMR (XRAM_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SLCR_APB 8roRead-only0x1A value of 1 indicates that the correctable timeout error is masked for the slave, SLCR APB
BANK3_APB 7roRead-only0x1A value of 1 indicates that the correctable timeout error is masked for the slave, bank3 APB
BANK3_AXI 6roRead-only0x1A value of 1 indicates that the correctable timeout error is masked for the slave, bank3 AXI
BANK2_APB 5roRead-only0x1A value of 1 indicates that the correctable timeout error is masked for the slave, bank2 APB
BANK2_AXI 4roRead-only0x1A value of 1 indicates that the correctable timeout error is masked for the slave, bank2 AXI
BANK1_APB 3roRead-only0x1A value of 1 indicates that the correctable timeout error is masked for the slave, bank1 APB
BANK1_AXI 2roRead-only0x1A value of 1 indicates that the correctable timeout error is masked for the slave, bank1 AXI
BANK0_APB 1roRead-only0x1A value of 1 indicates that the correctable timeout error is masked for the slave, bank0 APB
BANK0_AXI 0roRead-only0x1A value of 1 indicates that the correctable timeout error is masked for the slave, bank0 AXI