MSI_MASK_31_0 (CPM5_DMA_CSR) Register Description
| Register Name | MSI_MASK_31_0 |
|---|---|
| Relative Address | 0x0000000E50 |
| Absolute Address |
0x00FCE20E50 (CPM5_DMA0_CSR) 0x00FCEA0E50 (CPM5_DMA1_CSR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Register to control whether each MSI vector can cause the interrupt line [1] to be asserted in MSI Decode mode (attr_dma.msi_rx_decode_en = 1). A one in any location allows the MSI vector to assert the interrupt line[1]. This register initializes to all zeros. Therefore, by default no interrupt is generated for any event. This register is only implemented for Root Port. For non-Root Port, reads return 0 and writes are ignored. |
MSI_MASK_31_0 (CPM5_DMA_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| msi_31_0 | 31:0 | rwNormal read/write | 0x0 | Enables interrupts for MSI vector[n] events (data[5:0] == n) when bit[n] is set. EP returns 0. |