PL_EQ_TX_POSTCUR_E (CPM5_PCIE_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PL_EQ_TX_POSTCUR_E (CPM5_PCIE_ATTR) Register Description

Register NamePL_EQ_TX_POSTCUR_E
Relative Address0x00000002AC
Absolute Address 0x00FCE082AC (CPM5_PCIE0_ATTR)
0x00FCE882AC (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionTx POST-Cursor for PresetE
(Unused in PCIEB5)

This register should only be written to during reset of the PCIe block

PL_EQ_TX_POSTCUR_E (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 5:0rwNormal read/write0x0Tx POST-Cursor for PresetE
(Unused in PCIEB5)