TRIGCTRL2 (DBG_ELA_128) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

TRIGCTRL2 (DBG_ELA_128) Register Description

Register NameTRIGCTRL2
Relative Address0x0000000304
Absolute Address 0x00F0C60304 (DBG_APU_ELA)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionTRIGCTRL2

TRIGCTRL2 (DBG_ELA_128) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ALTCOMPSEL15rwNormal read/write0Select alternate comparison for trigger signal or trigger counter
ALTCOMP14:12rwNormal read/write0Trigger signal alternate coparison type select
CAPTID11:10rwNormal read/write0Captured transation ID options
COUNTBRK 9rwNormal read/write0Loop counter break
COUNTCLR 8rwNormal read/write0Clear the counter when advancing to the next trigger state
TRACE 7:6rwNormal read/write0Trace capture control
COUNTSRC 5rwNormal read/write0counter source select 0=ELACLK 1=trigger signal comparison
WATCHRST 4rwNormal read/write0Watchdog mode used to reset counter after a trigger signal comparison
COMPSEL 3rwNormal read/write0Comparison mode to enable counters and counter comparisons
COMP 2:0rwNormal read/write0Trigger Signal comparison type