attr_dma_axibar_as_5 (CPM5_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

attr_dma_axibar_as_5 (CPM5_DMA_ATTR) Register Description

Register Nameattr_dma_axibar_as_5
Relative Address0x00000001EC
Absolute Address 0x00FCE101EC (CPM5_DMA0_ATTR)
0x00FCE901EC (CPM5_DMA1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
Description32 or 64 bit address size

This register should only be written to during reset of the PCIe block

attr_dma_axibar_as_5 (CPM5_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x032 or 64 bit address size