ADDR_DECODE_IR_ENABLE (CPM5_INT_CSR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

ADDR_DECODE_IR_ENABLE (CPM5_INT_CSR) Register Description

Register NameADDR_DECODE_IR_ENABLE
Relative Address0x000000010C
Absolute Address 0x00FCA0010C (CPM5_INT_CSR)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInterrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)

ADDR_DECODE_IR_ENABLE (CPM5_INT_CSR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1woWrite-only0x0reserved
addr_decode_err 0woWrite-only0x0Status for an address decode error interrupt.